Present day DRAM memory elements contain a plurality of chip-internal timers, i.e. on-chip timers, which control different processes running on the DRAM element. Each of these timers is subject to inaccuracies, chip area consumption and the need for standby power. Since present day DRAM memory elements are specified to operate in a wide frequency range, e.g. from 83 MHz to 167 MHz, the clock supplied to the memory element from the outside cannot be used as a time basis for the control of internal processes. In particular the external clock cannot be used to ascertain particular time periods which must be controlled on the DRAM element itself, e.g. the time tRAS, which represents the time between the moment when a row (word line) is activated and the moment when this row can be precharged (closed). Another example is the time between the moment when data are written to an open row and the moment when this row should be closed; the time here is termed tWR.
Traditional DRAM elements normally contain chip-internal analog timer circuits to create the necessary delays, e.g. tRAS or tWR. As has been explained above, these timers must not use the externally provided clock as a time basis since the DRAM elements should be useable at different clock frequencies.
Alternative approaches have proved to be unsuitable. Such approaches include e.g. the addition of a bit line supervisor to monitor the reset voltages, but the required chip area is too large. On the other hand, the addition of a dummy bit line as reference leads to a high power consumption. Furthermore, the generation of a delay which exactly fulfils a necessary specification is too difficult to implement.
Registers have also been proposed which enable the memory control to report precisely the number of clock cycles which satisfy e.g. tRAS or TWR at the current operating frequency. This approach requires a register per timer and is therefore of no use for controlling all the timers. Also, with this approach, all the timers must be specified externally, which is not possible since not all the memory elements which satisfy a standard necessarily have the same timer structure.
As a result, today's DRAM memory elements or memory chips use independent analog delay elements to realize the above delay times, e.g. tRAS and tWR.